The Present and Future of Scanning Probe Technology for Advanced Semiconductor Device Manufacturing
김은파 박사
The Present and Future of Scanning Probe Technology for Advanced Semiconductor Device Manufacturing
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Eunpa Kim1,*, Yesol Song1, Yongjin Kwon1, Jongmin Park1, Minjung Shin1, Dongchul Ihm1
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1SAMSUNG ELECTRONICS Co., Ltd., Semiconductor R&D Center
1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do 18448 Korea
*eunpa.kim@samsung.com
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Since its introduction to the semiconductor industry in the '90s, scanning probe technology has seen increasing utilization and significance. Specifically, during the research and development phase of semiconductors, inline automated atomic force microscopy (AFM) equipment is extensively employed for both comprehensive analysis and providing rapid feedback within processes.[1] Although the current footprint of scanning probe microscopy (SPM) technology within semiconductor process metrology remains relatively modest, its impact and relevance are progressively escalating. SPM has become the de facto standard for nanometer-scale surface analysis such as roughness, step height, and depth measurement. There are no comparable technologies that match its precision. Historically, it has been integrated into etching, deposition, lithography, and chemical mechanical planarization (CMP) processes. Recently, significant demand is anticipated in bonding and advanced packaging sectors. To achieve the stringent planarity requirements post-CMP in bonding processes and manage the step heights within patterns, including copper (Cu) pads, dishing, erosion, and edge roll-off (ERO) management, there will be a considerable increase in the number of AFM and profiler-utilized processes, as well as the volume of wafers requiring measurement.[2,3] Furthermore, with ongoing scaling, the demand for high-resolution metrology will escalate, along with the increased adoption of various SPM modes capable of measuring electrical, mechanical, and magnetic properties.
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[1] M. Lee et.al., Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72722R (23 March 2009); https://doi.org/10.1117/12.813389
[2] T. -G. Kim et al., "In-line metrology for atomic resolution local height variation," 2017 28th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2017, pp. 267-272, doi: 10.1109/ASMC.2017.7969242.
[3] S. -A. Chew et al., "700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding," 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), Singapore, Singapore, 2022, pp. 334-337, doi: 10.1109/EPTC56328.2022.10013108.